A safety-critical avionics processing system may incorporate a multi-core processing environment (MCPE, also multi-core processing resource (MCPR)) within which multiple virtual machines may be maintained (e.g., by a system hypervisor), the virtual machines running a variety of guest operating systems (GOS) across several processing cores. The MCPE may connect to or control various devices via a Peripheral Component Interconnect (PCI) Express (PCIe) interface. Certification standards (e.g., DO-178B/C requirements governing safety-critical avionics software) may require partitioning of the MCPE to prevent catastrophic or hazardous interference within the system, such as a conflict between a first GOS and a second GOS for access to, or use of, a PCI device (or the second GOS interfering with the use of the PCI device by the first GOS). Accordingly, a PCI device (or its associated PCI controller, via which the PCI device interfaces with the MCPE) may be “owned” by a single GOS, to which any interrupts generated by the PCI device are directed. It may be desirable to allow multiple GOS to communicate with a given PCI device, even if one or more of the GOS do not “own” the PCI device.